What should Alpona build?
Describe a digital circuit in plain English. Alpona drafts the SystemVerilog, independently derives a behavioural model, writes a self-checking testbench from that model, and repairs the module against the compiler until it passes — every step streamed live.
Specification
Port names and widths are optional — the pipeline pins the interface from its own draft.
Pin the interface (optional)
Only if you need exact names or widths. Shown to every stage, like the harness's
public_interface.
Try:
Effort
Pipeline trace
finished stages collapse to a summary — click a bar to expand
1Propose
2Behavioural model
3Pre-compile
4Testbench
5Repair
Enter a spec and press Generate & verify.
You'll watch the model draft the module and derive a behavioural model at the same time, then build a self-checking testbench from that model and repair against the compiler — every stage streaming live.